Digi Times — Cadence Design Systems has announced that its Allegro system-in-package (SiP) and physical verification system (PVS) implementation technologies have been enabled for TSMC’s integrated fan-out (InFO) packaging technology. By providing an integrated solution that automates the design-rule checking (DRC) flow, the Allegro SiP design tools and PVS enable TSMC customers to shorten the InFO design and verification cycle.
Digi Times — Cadence Design Systems has announced an intellectual property (IP) portfolio for TSMC’s 10nm FinFET (N10) process. Cadence has already secured multiple design wins with this portfolio and is actively engaged with customers as adoption of TSMC’s leading-edge process grows. The initial deliveries of Cadence IP for the N10 process demonstrate a 20% power reduction and 50% area reduction compared to TSMC’s 16nm process technology, and are ideal for mobile and network infrastructure applications, Cadence indicated.
Cadence Design Systems has announced that it is collaborating with TSMC on the development of an Internet of Things (IoT) IP subsystem demonstration platform for TSMC’s ultra-low power (ULP) process. Targeting wearable, home automation, always-on and industrial control applications, the IP subsystem provides the opportunity to simplify IoT designs and accelerate the time to market for customers, Cadence said.